1. Technical Field
A method for manufacturing a semiconductor device is disclosed wherein: a source/drain impurity area is formed by using open base characteristics; an ion implantation of high density impurities for connecting the source/drain is performed; a first contact hole, a non-crystalline poly-silicon layer and a plasma enhanced magnetron-sputtered deposition (PMD) layer are formed consecutively; an ion implantation is performed; and then metal lines are formed. As a result, the size of the chip is reduced as the coding is performed by using the first contact hole without any coding area, damage to the semiconductor substrate is reduced and the leakage current is reduced as the first contact hole is formed before the of PMD layer. Further, the ON characteristic can be achieved by the reverse type ion implantation to the OFF characteristic, which is contrary to the case of a general read only memory (ROM) coding, and cutting of the metal line is minimized as the poly-silicon layer is formed under the metal line layer during the deposition of the metal lines.
2. Description of the Related Art
In general, a mask ROM is composed of the combination of depletion type transistors and enhancement type transistors.
The depletion type transistor has a minus threshold voltage according to the implantation of depletion ions, and maintains an ON state while the zero voltage is applied to the gate electrode thereof.
The enhancement type transistor has the threshold voltage of about 0.7 volt as the channel area thereof is counter-doped by a code ion implantation of the depletion type transistor, so it functions as an OFF-transistor of the mask ROM.
FIG. 1A is a graph for illustrating the operational characteristic of a general depletion type transistor, and FIG. 1B is a graph for illustrating the operational characteristic of a general enhancement type transistor.
As shown in FIGS. 1A and 1B, the channel is formed in the depletion type transistor even without applying the voltage to the gate electrode, and the channel is formed in the enhancement type transistor only when a voltage greater than the threshold voltage is applied to the gate electrode.
Herein below, the conventional method for manufacturing the semiconductor device is described with reference to the accompanying drawings.
FIGS. 2A through 2D are sectional views showing the conventional method for manufacturing a semiconductor device. As shown in FIG. 2A, a field area and an active area are defined on an n-type semiconductor substrate 11, and a plurality of field oxidation layers 12 are formed at certain intervals by performing a field ion implantation on the field area.
A photo process and a depletion ion implantation are then performed on the entire surface of the semiconductor substrate 11 including the field oxidation layers 12.
Those processes are performed using arsenic (As) ions that are n-type impurities, since the channel has to be n-type in the NMOS depletion mode.
Then, as shown in FIG. 2B, a gate insulation layer 13 and a polycrystalline silicon layer are formed on the entire surface of the semiconductor substrate 11 including the field oxidation layers 12, and a plurality of gate insulation layers 13 and gate electrodes 14 are formed on the active area of the semiconductor substrate 11 by a patterning and through a photolithography process.
Afterwards, an insulation layer is deposited on the entire surface of the semiconductor substrate 11 including the gate electrodes 14, and then the etch back is performed to form sidewall spacers 15 on both sides of each gate electrode 14.
Then, source/drain impurity areas 16 are formed at both sides of the gate electrode 14 on the semiconductor substrate 11 through the source/drain ion implantation process using the gate electrodes 14 and the sidewall spacers 15 as a mask.
After that, as shown in FIG. 2C, a code ion implantation is performed according to the request of a customer, for which areas other than the gate electrodes 13 are masked to manufacture an OFF transistor.
In other words, a photoresist 17 is coated on the entire surface of the semiconductor substrate 11 including the gate electrodes 14, and patterning through the exposure and development processes is performed so that only the gate electrodes 14 needed to form the OFF transistor are exposed.
Then, the code ion implantation is performed through the gate electrodes 14 by using the patterned photoresist 17 as a mask.
Accordingly, as shown in FIG. 2D, as the photoresist 17 is removed, the OFF transistor implemented by the ON transistor and the coding ion implantation is manufactured, which is the completion of the data coding.
However, such a conventional ROM coding method which implants ions on the active area results in current leakage.